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? semiconductor msm7508b/7509b 1/17 ? semiconductor msm7508b/7509b single rail codec general description the msm7508b and msm7509b are single-channel codec cmos ics for voice signals ranging from 300 to 3400 hz. these devices contain filters for a/d and d/a conversion. designed especially for a single-power supply and low-power applications, these devices are optimized for telephone terminals in isdn and digital wireless systems. the msm7508b/msm7509b are the transmission-clocks extended versions of the msm7508/ msm7509. it is recommended to use the msm7508/msm7509 for the transmission clocks of 64, 128, 256khz. features ? single power supply: +5 v 5% ? low power consumption operating mode: 17.5 mw typ. 37 mw max. power down mode: 1.5 mw typ. 3 mw max. ? itu-t companding law msm7508b: m -law msm7509b: a-law ? built-in pll eliminates a master clock ? transmission clock: 64/128/256/512/1024/2048 khz 96/192/384/768/1536/1544/200 khz ? adjustable transmit gain ? built-in reference voltage supply ? package options: 16-pin plastic dip (dip16-p-300-2.54-w1) (product name : MSM7508BRS) (product name : msm7509brs) 24-pin plastic sop (sop24-p-430-1.27-k) (product name : msm7508bgs-k) (product name : msm7509bgs-k) 28-pin plastic qfj (plcc) (qfj28-p-s450-1.27) (product name : msm7508bjs) (product name : msm7509bjs) note: the product names are indicated in pin configuration. e2u0013-28-81 this version: aug. 1998 previous version: nov. 1996
? semiconductor msm7508b/7509b 2/17 block diagram rc active bpf (8th) ad conv. transmit controller auto zero lpf (5th) da conv. pwd logic tpll receive controller pcmout xsync bclock rsync pcmin pdn v dd ag dg pwd + C ain+ ainC gsx sgc + C aout signal ground voltage ref. sg rpll
? semiconductor msm7508b/7509b 3/17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sgc sg aout v dd dg pdn rsync ain+ ainC gsx bclock ag xsync nc : no connect pin pcmin pcmout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 sgc nc sg aout v dd dg pdn ain+ ainC gsx ag bclock nc : no connect pin rsync pcmin xsync pcmout v dd nc nc nc nc nc nc nc nc : no connect pin dg pdn rsync pcmin nc pcmout xsync bclock ag nc nc nc nc aout nc sg sgc ain+ ainC gsx 4 3 2 1 28 27 26 12 13 14 15 16 17 18 nc nc nc nc nc nc nc nc nc 5 6 7 8 9 10 11 19 20 21 22 23 24 25 16-pin plastic dip 24-pin plastic sop 28-pin plastic qfj ( plcc ) pin configuration (top view)
? semiconductor msm7508b/7509b 4/17 ag analog signal ground. aout analog output. the output signal amplitude is a maximum of 2.4 v pp above and below the signal ground voltage level (v dd /2). the output load resistance is a minimum of 20 k w . during power saving or power down mode, the output of aout is at the voltage level of signal ground. pin and functional descriptions ain+, ainC, gsx transmit analog input and transmit level adjustment. ain+ is a non-inverting input to the op-amp; ainC is an inverting input to the op-amp; gsx is connected to the output of the op-amp and is used to adjust the level, as shown below. when not using ainC and ain+, connect ainC to gsx and ain+ to sg. during power saving and power down modes, the gsx output is in a high impedance state. C + ainC ain+ c1 analog input 1) inverting input type r1 : variable r2 > 20 k w c1 > 1/(2 3.14 30 r1) gain = r2/r1 10 r2 gsx sg + C ain+ ainC 2) non inverting input type r3 > 20 k w r4 > 20 k w r5 > 50 k w c2 > 1/ (2 3.14 30 r5) gain = 1 + r4 / r3 10 r4 gsx sg c2 analog input r3 r5 r1
? semiconductor msm7508b/7509b 5/17 v dd power supply for +5 v. pcmin pcm signal input. a serial pcm signal input to this pin is converted to an analog signal in synchronization with the rsync signal and bclock signal. the data rate of the pcm signal is equal to the frequency of the bclock signal. the pcm signal is shifted at a falling edge of the bclock signal and latched into the internal register when shifted by eight bits. the start of the pcm data (msd) is identified at the rising edge of rsync. bclock shift clock signal input for the pcmin and pcmout signal. the frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048 khz. setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. rsync receive synchronizing signal input. eight required bits are selected from serial pcm signals on the pcmin pin by the receive synchronizing signal. signals in the receive section are synchronized by this synchronizing signal. this signal must be synchronized in phase with the bclock. the frequency should be 8 khz 50 ppm to guarantee the ac characteristics which are mainly frequency characteristics of the receive section. however, if the frequency characteristic of an applied system is not specified exactly, this device can operate in the range of 8 to 10 khz, but the electrical characteristics in this specification are not guaranteed. setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. xsync transmit synchronizing signal input. the pcm output signal from the pcmout pin is output in synchronization with this transmit synchronizing signal. this synchronizing signal triggers the pll and synchronizes all timing signals of the transmit section. this synchronizing signal must be synchronized in phase with bclock. the frequency should be 8 khz 50 ppm to guarantee the ac characteristics which are mainly frequency characteristics of the transmit section. however, if the frequency characteristic of an applied system is not specified exactly, this device can operate in the range of 8 to 10 khz, but the electrical characteristics in this specification are not guaranteed. setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state.
? semiconductor msm7508b/7509b 6/17 dg ground for the digital signal circuits. this ground is separate from the analog signal ground. the dg pin must be connected to the ag pin on the printed circuit board to make a common analog ground. pdn power down control signal. a logic "0" level drives both transmit and receive circuits to a power down state. pcmout pcm signal output. the pcm output signal is output from msd in a sequential order, synchronizing with the rising edge of the bclock signal. msd may be output at the rising edge of the xsync signal, based on the timing between bclock and xsync. this pin is in a high impedance state except during 8-bit pcm output. it is also in a high impedance state during power saving or power down modes. a pull-up resistor must be connected to this pin because its output is configured as an open drain. this device is compatible with the itu-t recommendation on coding law and output coding format. the msm7509b (a-law) outputs the character signal, inverting the even bits. input/output level +full scale +0 C0 Cfull scale pcmin/pcmout msm7508b ( m -law) msd 1000 0000 1111 1111 0111 1111 0000 0000 msm7509b (a-law) msd 1010 1010 1101 0101 0101 0101 0010 1010 sg signal ground voltage output. the output voltage is 1/2 of the power supply voltage. the output drive current capability is 300 m a. this pin provides the sg level for codec peripherals. this output voltage level is undefined during power saving or power down modes. sgc used to generate the signal ground voltage level by connecting a bypass capacitor. connect a 0.1 m f capacitor with excellent high frequency characteristics between the ag pin and the sgc pin.
? semiconductor msm7508b/7509b 7/17 absolute maximum ratings recommended operating conditions parameter power supply voltage analog input voltage digital input voltage storage temperature symbol v dd v ain v din t stg condition rating 0 to 7 C0.3 to v dd + 0.3 C0.3 to v dd + 0.3 C55 to +150 unit v v v c parameter symbol power supply voltage analog input voltage input high voltage input low voltage clock frequency sync pulse frequency clock duty ratio digital input rise time digital input fall time transmit sync pulse setting time receive sync pulse setting time sync pulse width pcmin set-up time pcmin hold time analog output load digital output load analog input allowable dc offset allowable jitter width v dd v ain v ih v il f c f s d c t ir t if t xs t ws t ds t dh r al r dl v off t sx t rs t sr c al c dl condition connect ainC and gsx xsync, rsync, bclock, pcmin, pdn bclock xsync, rsync bclock xsync, rsync, bclock, pcmin, pdn bclock ? xsync, see timing diagram xsync, rsync aout pull-up resistor transmit gain stage, gain = 1 xsync, rsync, bclock xsync ? bclock, see timing diagram bclock ? rsync, see timing diagram rsync ? bclock, see timing diagram aout, gsx gsx transmit gain stage, gain = 10 min. typ. max. unit 4.75 2.2 0 64, 128, 256, 512, 1024, 2048, 96, 192, 384, 768, 1536, 1544, 200 7.0 40 100 1 bclk 100 100 20 0.5 C100 100 100 100 20 C10 5.0 8.0 50 5.25 2.4 v dd 0.8 10.0 60 50 50 100 +100 500 100 100 +10 v v pp v v khz % ns ns ns m s ns ns k w k w mv ns ns ns ns pf pf k w mv khz voltage must be fixed operating temperature ta c C10 +25 +70
? semiconductor msm7508b/7509b 8/17 electrical characteristics dc and digital interface characteristics parameter power supply current input high voltage input low voltage high level input leakage current low level input leakage current digital output low voltage digital output leakage current input capacitance symbol i dd1 i dd2 i dd3 v ih v il i ih i il v ol i o condition operating mode power-save mode, pdn = 1, sync ? off power-down mode, pdn = 0 pull-up resistance > 500 w min. 2.2 0.0 0.0 typ. 3.5 0.3 0.8 0.2 max. 7.0 0.5 1.2 v dd 0.8 2.0 0.5 0.4 10 unit ma ma v v m a m a v m a c in 5pf (v dd = +5 v 5%, ta = C10c to +70c) ma analog output offset veltage analog input resistance v off aout with respect to sg C100 +100 mv r in ain+, ainC 10 m w
? semiconductor msm7508b/7509b 9/17 ac characteristics condition (v dd = +5 v 5%, ta = C10c to +70c) parameter symbol min. typ. max. unit transmit frequency response loss t1 level (dbm0) 60 20 26 db freq. (hz) loss t2 300 C0.15 +0.07 +0.20 db loss t3 1020 reference db 0 loss t4 2020 C0.15 C0.04 +0.20 db loss t5 3000 C0.15 +0.06 +0.20 db loss t6 3400 0 0.40 0.80 db receive frequency response loss r1 300 C0.15 C0.03 +0.20 db loss r2 1020 reference db loss r3 2020 C0.15 C0.02 +0.20 db 0 loss r4 3000 C0.15 +0.15 +0.20 db loss r5 3400 0.0 0.56 0.80 db sd t1 35 43 3 sd t2 35 41 0 sd t3 35 38 C30 transmit signal to distortion ratio 1020 db sd t4 28 30.0 C40 *1 sd t5 23 25.0 C45 sd r1 36 43 3 sd r2 36 41 0 sd r3 36 40 C30 receive signal to distortion ratio 1020 db sd r4 30 33.5 C40 *1 sd r5 25 30 C45 transmit gain tracking gt t1 C0.2 +0.01 +0.2 gt t2 reference gt t3 1020 C0.2 0.0 +0.2 db C40 gt t4 C0.4 C0.03 +0.4 gt t5 C1.2 +0.15 +1.2 3 C10 C50 C55 receive gain tracking gt r1 C0.2 0 +0.2 gt r2 reference gt r3 1020 C0.2 C0.06 +0.2 db gt r4 C0.4 C0.20 +0.4 gt r5 C0.8 C0.27 +0.8 C40 3 C10 C50 C55 29.5 24.5 32 27 *2 *2 24 *1 psophometric filter is used *2 upper is specified for the msm7508b, lower for the msm7509b
? semiconductor msm7508b/7509b 10/17 ac characteristics (continued) absolute level (initial difference) nidle t dbmop nidle r C76.5 av t 0.5671 0.6007 0.6363 av r 0.5671 0.6007 0.6363 vrms 1020 absolute delay 0 td 1020 0.60 ms 0 a to a bclock = 64 khz transmit group delay tgd t1 0.19 0.75 tgd t2 0.11 0.35 tgd t3 0.02 0.125 0 tgd t4 0.05 0.125 ms *4 0.07 tgd t5 0.75 receive group delay 0.00 0.75 0.00 0.00 0.125 ms 0 0.09 0.125 0.12 0.75 C74 idle channel noise ain = sg *3 *2 500 600 1000 2600 2800 crosstalk attenuation cr t 7585 cr r 77 1020 db 0 trans ? recv recv ? trans tgd r1 tgd r2 tgd r3 tgd r4 tgd r5 500 600 1000 2600 2800 *4 70 0.35 condition (v dd = +5 v 5%, ta = C10c to +70c) parameter symbol min. typ. max. unit level (dbm0) freq. (hz) C72.5 C70 C70.5 C69 *2 *1 *1 psophometric filter is used *2 upper is specified for the msm7508b, lower for the msm7509b *3 msm7508b: all "0" code to pcmin, msm7509b: "11010101" to pcmin *4 minimum value of the group delay distortion
? semiconductor msm7508b/7509b 11/17 ac characteristics (continued) dis 4.6 khz to 30 32 db digital output delay time t sd 50 200 t xd1 50 200 t xd2 50 200 t xd3 50 200 ns discrimination 0 0 to 4000 hz c l = 100 pf + 1 lsttl s 300 to C37.5 C35 dbmo out-of-band spurious 0 4.6 khz to imd fa = 470 C52 C35 dbmo intermodulation distortion C4 2fa C fb psr t 30db power supply noise rejection ratio 50 mv pp psr r 72 khz 3400 fb = 320 100 khz condition (v dd = +5 v 5%, ta = C10c to +70c) parameter symbol min. typ. max. unit level (dbm0) freq. (hz) 0 khz to 50 khz *5 *5 the measurement under idle channel noise
? semiconductor msm7508b/7509b 12/17 timing diagram pcm data input/output timing bclock 12345678910 xsync pcmout d2 d3 d4 d5 d6 d7 d8 msd t xs t sx t ws t sd t xd1 t xd2 t xd3 bclock 12345678910 rsync pcmin d2 d3 d4 d5 d6 d7 msd t rs t sr t ws t ds t dh d8 transmit timing receive timing 11 when t xs 1/2 ? fc, the delay of the msd bit is defined as t xd1 . when t sx 1/2 ? fc, the delay of the msd bit is defined as t sd . 11
? semiconductor msm7508b/7509b 13/17 application circuit pcmout ainC gsx analog input aout 10 m f pcm signal output pcm data input pcm shift clock input 8 khz sync signal input power down control input 0.1 m f 1 k w "1" = operation "0" = power down msm7508b/7509b 0 to 20 w ain+ pcmin bclock analog output +5 v digital interface xsync pdn sgc ag dg v dd 0 v +5 v sg rsync 1 m f + C the analog output signal has an amplitude of 1.2 v above and below the offset voltage level of v dd /2.
? semiconductor msm7508b/7509b 14/17 recommendations for actual design ? to assure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. ? connect the ag pin and the dg pin each other as close as possible. connect to the system ground with low impedance. ? mount the device directly on the board when mounted on pcbs. do not use ic sockets. if an ic socket is unavoidable, use the short lead type socket. ? when mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave source such as power supply transformers surround the device. ? keep the voltage on the v dd pin not lower than C0.3 v even instantaneously to avoid latch- up phenomenon when turning the power on. ? use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices.
? semiconductor msm7508b/7509b 15/17 (unit : mm) package dimensions dip16-p-300-2.54-w1 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.00 typ.
? semiconductor msm7508b/7509b 16/17 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). sop24-p-430-1.27-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.58 typ. mirror finish
? semiconductor msm7508b/7509b 17/17 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfj28-p-s450-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin cu alloy solder plating 5 m m or more 1.00 typ. spherical surface

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